This patent application relates to the field of circuit simulation, and more precisely to more easily performing verification tasks for mixed-signal circuit designs.
Verification is an important step in the process of designing and creating an electronic product. Verification helps ensure that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to verify circuit designs, including simulation. Simulation verifies a design by monitoring computed behaviors of the design with respect to test stimuli. A variety of commercially offered software programs are available for circuit simulation.
In digital circuit design, “coverage” is the relative amount of user-defined circuit design goals that are met as a result of applied predetermined test stimuli. Historically, coverage in computer science referred to detecting the full execution of lines in source code, but for circuit design the focus is more typically on the execution of various functional scenarios or achievement of various circuit states. A set of test stimuli may thus be designed to exercise the intended functionality of a circuit to some extent, typically by causing the various required state changes to occur. Verification may further include determining whether such state changes occur within certain time constraints.
Coverage definition has become a popular way to ensure the completeness of verification. Ideally, a circuit will fully function as intended, so all the performance goals of a test plan are met. Predefined coverage goals ensure that the verification task achieves a sufficiently high coverage score. Goals that are determined to not be completely met may help a designer identify design problems and accordingly modify a circuit stimulus to correct those problems and thus improve coverage. Specialized hardware description languages such as SystemVerilog and “e” for example are widely used for digital circuit verification purposes. Coverage goals are defined in such languages, and a simulator collects the coverage information.
Analog circuit design is conceptually different however, as analog circuits operate in a continuous value space. There is no discrete state space as defined in digital circuits. Analog circuits are often not based on hardware description languages that describe many digital circuits. Analog circuits are instead typically described (e.g., in netlists for SPICE-like simulators) by a set of nodes interconnected by various components, with node voltages and component currents that require calculation. Such circuits are not always amenable to a clear separation into functional blocks handling binary signals, as in digital circuit design and simulation.
FIGS. 1A-1B show an exemplary analog circuit design 100 and a corresponding non-discrete state space. In this case, as shown in FIG. 1A, an input voltage source 102 drives inductor current IL through a resistor 104 and an inductor 106. The inductor current then splits to travel through a diode 108 and a capacitor 110 that are connected in parallel to ground. The inductor current IL and the capacitor voltage VC may be tightly interrelated as shown in FIG. 1B. The behavior of the circuit shown may be highly time-dependent as well.
Analog circuits may therefore be generally more difficult to describe and manage at different layers of design abstraction than digital circuits. Analog circuit design is thus often much more time-consuming both in terms of simulation time and designer activity. Although progress has been made in development of behavioral models for analog circuit blocks, no clear concept that parallels coverage as in digital design has been developed for analog or mixed-signal circuits (i.e., those having both analog and digital circuitry integrated together).
Even the development of behavioral models is impeded by this same conceptual difficulty. Behavioral models are widely used to speed up verification tasks because they can be simulated faster than more detailed lower-level reference models. However, such behavioral models need to be properly validated to ensure correct verification results. To accomplish this, simulation results of a behavioral model are compared against the simulation results of a more detailed reference design, and must match to within predefined tolerances. Behavioral model validation may be incomplete however, if some behaviors of the behavioral model are not exercised to the point of adequate coverage. The validation results are thus only as good as the simulation testbench and the extent to which it exercises the behavioral model.
Accordingly, the inventors have developed a novel way to provide circuit designers with coverage information for analog/mixed-signal circuit designs.